IEEE International Conference on Parallel and Distributed Systems (IEEE ICPADS 2020)
Data Processing
A social link based private storage cloud
Michalis Konstantopoulos, Nikos Chondros and Mema Roussopoulos
Enabling Generic Verifiable Aggregate Query on Blockchain Systems
Yanchao Zhu, Zhao Zhang, Cheqing Jin, and Aoying Zhou
SrSpark: Skew-resilient Spark based on Adaptive Parallel Processing
Yijie Shen, Jin Xiong and Dejun Jiang
Optimizing Multi-way Theta Join for Data Skew in Sub-Second Stream Computing
Xiaopeng Fan, Xinchun Liu, Yang Wang, Youjun Wang, and Jing Li
Session Chair
Weigang Wu (Sun Yat-sen University)
Resource and Data Management
OOOPS: An Innovative Tool for IO Workload Management on Supercomputers
Lei Huang and Si Liu
URFS: A User-space Raw File System based on NVMe SSD
Yaofeng Tu, Yinjun Han, Zhenghua Chen, Zhengguang Chen and Bing Chen
DyRAC: Cost-aware Resource Assignment and Provider Selection for Dynamic Cloud Workloads
Yannis Sfakianakis, Manolis Marazakis and Angelos Bilas
WMAlloc: A Wear-Leveling-Aware Multi-Grained Allocator for Persistent Memory File Systems
Shun Nie, Chaoshu Yang, Runyu Zhang, Wenbin Wang, Duo Liu and Xianzhang Chen
Session Chair
Huawei Huang (Sun Yat-sen University)
Secure and Reliable Systems
Optimizing Complex OpenCL Code for FPGA: A Case Study on Finite Automata Traversal
Marziyeh Nourian, Mostafa Eghbali Zarch and Michela Becchi
This paper explores this problem on finite automata traversal. In particular, we consider an OpenCL NFA traversal kernel optimized for GPU but exhibiting FPGA-friendly characteristics, namely: limited memory requirements, lack of synchronization, and SIMD execution. We explore a set of structural code changes, custom and best-practice optimizations to retarget this code to FPGA. We showcase the effect of these optimizations on an Intel Stratix V FPGA board using various NFA topologies from different application domains. Our evaluation shows that, while the resource requirements of the original code exceed the capacity of the FPGA in use, our optimizations lead to significant resource savings and allow the transformed code to fit the FPGA for all considered NFA topologies. In addition, our optimizations lead to speedups up to 4x over an already optimized code-variant aimed to fit the NFA traversal kernel on FPGA. Some of the proposed optimizations can be generalized for other applications and introduced in OpenCL-to-FPGA compiler.
FastCredit: Expediting Credit-based Proactive Transports in Datacenters
Dezun Dong, Shan Huang, Zejia Zhou, Wenxiang Yang and Hanyi Shi
Based on this observation, this paper makes the first attempt to accelerate short-flow scheduling in credit-based proactive transport, and proposed FastCredit. FastCredit can be used as a general building block to expedite short flows in creditbased proactive transports. In FastCredit, we schedule credit transmission at both receivers and switches to indirectly perform flow scheduling, and develop a mechanism to mitigate credit waste and improve network goodput. Compared to the stateof- the-art credit-based transport protocol, FastCredit reduces average flow completion time to 0.78x and greatly improves the short flow transmission latency to 0.51x in realistic workloads. Especially, FastCredit reduces average flow completion time to 0.76x under incast circumstances and 0.62x in many-to-one traffic mode. Furthermore, FastCredit still maintains the advantages of short queue and high throughput.
Proactive Failure Recovery for Stateful NFV
Zhenyi Huang and Huawei Huang
TEEp: Supporting Secure Parallel Processing in ARM TrustZone
Zinan Li, Wenhao Li, Yubin Xia and Binyu Zang
Session Chair
Yu Huang (Nanjing University)
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